|No Of Layers::||2 Layer||Material::||FR4 TG130|
|PCB Thickness::||0.8 MM||Solder Mask Colour::||Green|
|Surface Technics::||Immersion Gold 1U'||Copper Thickness:||35 UM|
Immersion Gold 2 Layer PCB,
0.8 MM Thickness 2 Layer PCB,
2 Layer FR4 Printed Circuit Board 0.8 MM Thickness Used In Beacon
1 2 Layer FR4 substrate material printed circuit board.
2 Double layer copper, copper thickness is 35um/35um.
3 Finished pcb thickness is 1.2mm.
4 PCB drawing size is 128.82mm*96.14mm/6pcs
5 Immersion Gold treatment
6 2 layer pcb with 6/6mil min line space and width.
7 Green solder mask and white silkscreen.
8 Need customer to send us the gerber file or PCB file
|1||Layer Count||1-24 Layers|
|3||Finished Board Max Size||700mm*800mm|
|4||Finished Board Thickness Tolerance||+/-10% +/-0.1(<1.0mm)|
|6||Major CCL Brand||KB/NanYa/ITEQ/ShengYi/Rogers Etc|
|7||Material Type||FR4,CEM-1,CEM-3,Aluminum,Copper, Ceramic, PI, PET|
|8||Drill Hole Diameter||0.1mm-6.5mm|
|9||Out Layer Copper Thickness||1/2OZ-8OZ|
|10||Inner Layer Copper Thickness||1/3OZ-6OZ|
|12||PTH Hole Tolerance||+/-3mil|
|13||NPTH Hole Tolerance||+/-1mil|
|14||Copper Thickness of PTH Wall||>10mil(25um)|
|15||Line Width And Space||2/2mil|
|16||Min Solder Mask Bridge||2.5mil|
|17||Solder Mask Alignment Tolerance||+/-2mil|
|19||Max Gold Thickness||200u'(0.2mil)|
|20||Thermal Shock||288℃, 10s, 3 times|
|22||Test Capability||PAD Size min 0.1mm|
|24||Surface Treatment||OSP, ENIG,HASL, Plating Gold, Carbon Oil,Peelable Mask etc|
Q1: What is PCB Interconnect Stress Testing (IST)?
A1: PCB Interconnect Stress Testing (IST) is a process to identify failures in vias and multilayer interconnects by consistently monitoring resistance variations. This testing is performed on a PCB test coupon, where it undergoes several thermal cycles. These thermal cycles are created by applying current to a specific test coupon. IST is a way to check the reliability of the PCB board. This process assesses both vias and multilayer interconnects. The via barrels and inner layer junctions are exposed to current repetitively until the failure is not identified. It can be performed easily within the temperature ranges from 25 to 150 degrees Celsius. The motive of IST testing is to check whether the board design is responsible for failure.
Reliability means how efficiently a PCB board can perform its desired functions under stated conditions. IST testing is important for all levels, from PCB manufacturers, assemblers to end-users. This method is registered in IPC under IPC-TM-650 regulation. It is used to characterize the total interconnects in a PCB and detects separation/ cracks between inner layer to via barrel.
Advantages of IST PCB Testing
The IST system is designed to monitor the ability of PCB interconnects to withstand the thermal stress while performing an end application. It can be performed on two stages, either on the manufactured PCB or on the assembled one. In short, it helps to identify the degrade rate of the interconnects. The difference between the resistance values before and after the testing is calculated for different thermal cycles so that an optimum rejection criterion can be concluded. The IST methodology allows the user to determine when a defect starts to develop and its propagation rate.
During testing, the IST system applies a DC current to the PCB coupon. This current increases the temperature of the metal and its adjacent materials. The temperature to be applied to the coupon is directly proportional to the total resistance and the amount of current passed through the tracks, pads, and holes. The IST system keeps on raising the temperature until it reaches 150 degrees celsius (which is slightly below the glass transition temperature of the base material). Once the desired temperature achieved, it stops the current and forced cooling begins. This sums up the first cycle. After this, the system monitors for resistance variation resulting in via cracking or failure of inner layer interconnects.
The IST testing system keeps repeating this process until the pre‐determined rejection criterion is achieved. Coupon rejection can be based on a maximum number of cycles, or a percentage increase within each interconnects' circuits elevated resistance (usually a 10% increase from the starting resistance). If the interconnect quality is good, then it may survive around hundreds of such thermal cycles.